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LPC3240 Datasheet(PDF) 62 Page - NXP Semiconductors |
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LPC3240 Datasheet(HTML) 62 Page - NXP Semiconductors |
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62 / 80 page ![]() LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.1 — 24 June 2014 62 of 80 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Fig 10. DDR control timing parameters EMC_CLK EMC control and address signals 002aae436 tCK tCH tCL td(AV); td(V)ctrl th(A); th(ctl) valid Fig 11. DDR write timing parameters command EMC_D[31:0], EMC_DQM[3:0] tDQSL tDQSH tDQSS th(Q) EMC_DQS[1:0] EMC_CLK 002aae437 WRITE tsu(Q) tDSH tDSS (1) The delay of the EMC_DQS[1:0] signal is determined by the DQS_DELAY settings. See LPC32x0 User manual, External Memory Controller Chapter, section DDR DQS delay calibration for details on configuring this value. Fig 12. DDR read timing parameters EMC_CLK command EMC_D[31:0] tsu(D) EMC_DQS[1:0] 002aae438 th(D) READ delayed EMC_DQS[1:0](1) td(DQS) |
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