LPC3240 datasheet(64/80 Pages) NXP

64 / 80 page

LPC3220_30_40_50

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Product data sheet

Rev. 2.1 — 24 June 2014

64 of 80

NXP Semiconductors

LPC3220/30/40/50

16/32-bit ARM microcontrollers

11.7 MLC NAND flash memory controller

[1]

THCLK = 1/HCLK

[2]

CEAD = bit field TCEA_DELAY[1:0] in register MLC_TIME_REG[25:24]

[3]

WL = bit field WR_LOW[3:0] in register MLC_TIME_REG[3:0]

[4]

WH = bit field WR_HIGH[3:0] in register MLC_TIME_REG[7:4]

[5]

RL = bit field RD_LOW[3:0] in register MLC_TIME_REG[11:8]

[6]

RH = bit field RD_HIGH [3:0] in register MLC_TIME_REG[15:12]

[7]

RHZ = bit field NAND_TA[2:0] in register MLC_TIME_REG[18:16]

[8]

BD = bit field BUSY_DELAY[4:0] in register MLC_TIME_REG[23:19]

Fig 14.

SD card pin interface timing

002aae441

MS_SCLK

MS_DIO[3:0](O)

MS_DIO[3:0] (I)

td(QV)

th(D)

tsu(D)

Tcy(clk)

th(Q)

MS_BS (O)

MS_BS (I)

Table 17.

Dynamic characteristics of the MLC NAND flash memory controller

Tamb = 40 C to +85 C.

Symbol

Parameter

Min

Typ

Max

Unit

tCELREL

CE LOW to RE LOW time

[1][2]

-THCLK  CEAD

-ns

tRC

RE cycle time

[1][5][6]

-THCLK  (RL + 1) + THCLK  (RH  RL)-

tREH

RE HIGH hold time

[1][5][6]

-THCLK  (RH  RL)-

tRHZ

RE HIGH to output high-impedance time [1][5][7]

-THCLK  (RH  RL) + THCLK  RHZ

-ns

tRP

RE pulse width

[1][5]

-THCLK  (RL + 1)

tREHRBL

RE HIGH to R/B LOW time

[1][8]

-THCLK  BD

-ns

tWB

WE HIGH to R/B LOW time

[1][8]

-THCLK  BD

-ns

tWC

WE cycle time

[1][3][4]

-THCLK  (WL + 1) + THCLK  (WH  WL)-

tWH

WE HIGH hold time

[1][3][4]

-THCLK  (WH  WL)-

tWP

WE pulse width

[1][3]

-THCLK  (WL + 1)

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