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LPC3240 Datasheet(PDF) 53 Page - NXP Semiconductors |
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LPC3240 Datasheet(HTML) 53 Page - NXP Semiconductors |
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53 / 80 page ![]() LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.1 — 24 June 2014 53 of 80 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 10.1 Minimum core voltage requirements Figure 4 shows the minimum core supply voltage that should be applied for a given core frequency on pin VDD_CORE to ensure stable operation of the LPC3220/30/40/50. 10.2 Power supply sequencing The LPC32x0 has no power sequencing requirements, that is, VDD(1V2), VDD(EMC), VDD(IO), and VDDA(3V3) can be switched on or off independent of each other. An internal circuit ensures that the system correctly powers up in the absence of core power. During IO power-up this circuit takes care that the system is powered in a defined mode. The same is valid for core power-down. 10.3 Power consumption per peripheral [1] All three Ethernet clocks are in enabled in the MAC_CLK_CTRL register (see LPC32x0 User manual). Fig 4. Minimum required core supply voltage for different core frequencies core frequency (MHz) 160 280 240 200 002aae872 1.0 1.2 1.4 0.8 VDD_CORE (V) Table 9. Power consumption per peripheral Tamb =25 C; CPU clock = 208 MHz; I-cache/D-cache, MMU disabled; VDD_CORE = 1.2 V; VDD(IO) = 1.8 V; USB AHB, IRAM, and IROM clocks always on; all peripherals are at their default state at reset. Peripheral clocks are disabled except for peripheral measured. Peripheral IDD(run) / mA High-speed UART (set to 115 200 Bd (8N1)) 0.3 I2C-bus 0.3 SSP 0.6 I2S0.5 DMA 6.3 EMC 7.3 Multi-level NAND controller 1.4 Single-level NAND controller 0.3 LCD 5.6 Ethernet MAC[1] 2.9 |
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