LPC3240 datasheet(61/80 Pages) NXP

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LPC3220_30_40_50

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Product data sheet

Rev. 2.1 — 24 June 2014

61 of 80

NXP Semiconductors

LPC3220/30/40/50

16/32-bit ARM microcontrollers

11.4 DDR SDRAM controller

[1]

All values valid for EMC pads set to fast slew rate at 1.8 V unless otherwise specified (see SDRAMCLK_CTRL register in the LPC32x0

User manual).

[2]

CMD_DLY = COMMAND_DELAY bit field in SDRAMCLK_CTRL[18:14] register, see External Memory Controller (EMC) chapter in

LPC32x0 User manual.

[3]

Applies to signals EMC_DQM[3:0], EMC_DYCS[1:0], EMC_RAS, EMC_CAS, EMC_WR, EMC_CKE[1:0].

[4]

DQS_DELAY, see LPC32x0 User manual, External Memory Controller Chapter, Section 8 DDR DQS delay calibration for details on

configuring this value.

[5]

Test conditions for measurements: Tamb = 40 C to +85 C; operating frequency range foper = 52 MHz to 133 MHz; EMC_DQM[3:0] and

EMC_D[31:0] driving 2 inches of 50

 characteristic impedance trace with 10 pF capacitive load; no external source series termination

resistors used. EMC pads set to fast slew rate at 1.8 V or 2.5 V (see SDRAMCLK_CTRL register in the LPC32x0 User manual).

Table 14.

EMC DDR SDRAM memory interface dynamic characteristics[1]

CL =25 pF, Tamb =25 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typical

Max

Unit

foper

operating frequency

104

133

MHz

tCK

clock cycle time

7.5

9.6

tCL

CK LOW-level width

0.5

 t

-ns

tCH

CK HIGH-level width

0.5

 t

-ns

td(V)ctrl

control valid delay time

[2][3]

(CMD_DLY

 0.25) + 1.5

th(ctrl)

control hold time

[2][3]

(CMD_DLY

 0.25)  1.5

td(AV)

address valid delay time

[2]

(CMD_DLY

 0.25) + 1.5

th(A)

address hold time

[2]

(CMD_DLY

 0.25)  1.5

tsu(Q)

data output set-up time

EMC_D[31:0]

and

EMC_DQM[3:0]

EMC_DQS[1:0]

out

[5]

0.08

 t

0.15

 t

0.25

 t

th(Q)

data output hold time

EMC_D[31:0]

and

EMC_DQM[3:0]

EMC_DQS[1:0]

out

[5]

0.25

 t

0.35

 t

0.42

 t

tDQSH

DQS HIGH time

for WRITE

command

-0.5

 t

-ns

tDQSL

DQS LOW time

for WRITE

command

-0.5

 t

-ns

tDQSS

WRITE command to first DQS latching

transition time

for DQS out

tCK + 0.7

tDSS

DQS falling edge to CK set-up time

for DQS in

0.5

 t

-ns

tDSH

DQS falling edge hold time from CK

for DQS in

0.5

 t

-ns

td(DQS)

DQS delay time

for DQS in

[4]

-DQS_DELAY

tsu(D)

data input set-up time

0.3

th(D)

data input hold time

0.5

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