LAN8804D datasheet(38/89 Pages) MICROCHIP

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LAN8804D

DS00003591K-page 38

Data Select 1 register (GPIO_DATA_SEL1) or the General Purpose IO Data Select 2 register (GPIO_DATA_SEL2). The

SOF pulse is always active high. For details on SOF detection timing, refer to Section 6.6.8, "GPIO SOF Detection Tim-

ing".

The SOF pulse can also be configured to detect 802.3-2018 SMDs. When the SOF_preemption_enable bits in MMD2

continuation frame: SMD-V (0x07), SMD-R (0x19), SMD-E (0xD5) and SMD-S[0,1,2,3] (0xE6, 0x4C, 0x7F or 0xB3).

When the SOF_preemption_enable bits are set to ‘11’, the SOF pulse is also generated for the continuation SMD val-

ues: SMD-C[0,1,2,3] (0x61, 0x52, 0x9E or 0x2A).

5.11

Signal Quality Index

5.11.1

BACKGROUND

MLT-3 modulation is used for data transmission in 100BASE-TX and PAM5 modulation is used for data transmission in

1000BASE-T.

Logically, 100BASE-TX (MLT-3) and 1000BASE-T (PAM5) have signal values of {-1, 0, +1} and {-2, -1, 0, +1, +2},

respectively. These logic levels are mapped to slicer reference levels of {-128, 0, 128} for 100BASE-TX and {-128, -64,

0, 64, 128} for 1000BASE-T. The middle points (the compare thresholds) are {-64, 64} for 100BASE-TX and are {-96, -

32, 32, 96} for 1000BASE-T.

Ideally, each receive data sample would be the maximum distance from the compare thresholds, with error values of 0.

But because of noise and imperfection in real applications, the sampled data may be off from its ideal. The closer to the

compare threshold, the worse the signal quality.

The slicer error is a measurement of how far the processed data is off from its ideal location. The largest instantaneous

slicer error for 1000BASE-T is ±32. The largest instantaneous slicer error for 100BASE-TX is ±64.

A higher absolute slicer error means a degraded signal receiving condition.

5.11.2

NON OPEN ALLIANCE LOW PASS FILTERED ERROR

With this method, the slicer error is converted into an absolute value and then filtered by a programmable low pass filter.

This is similar to taking the average of absolute slicer error over a long moving time window.

This mode is enabled by setting the sqi_enable bit in the Dynamic Channel Quality (DCQ) Configuration register.

For each data sample, the difference between the absolute slicer error (scaled by x2 (before squaring) for

1000BASE-T) and the current filtered value is added back into the current filtered value. The sqi_squ_mode_en bit in

the DCQ Configuration register is used to square the (scaled) slicer error.

The sqi_kp field in the DCQ Configuration register sets the weighting of the add back as a divide by 2^sqi_kp, effectively

setting the filter bandwidth. As the sqi_kp value is increased, the weighing is decreased, and the mean slicer error value

takes a longer time to settle to a stable value. Also, as the sqi_kp value is increased, there will be less variation in the

mean slicer error value reported.

The filtered error value is saved every 1.0 ms (125,000 symbols).

In order to capture the current error value, the DCQ Read Capture bit in the DCQ Configuration register needs to be

written as a high with the desired cable pair specified in the DCQ Channel Number field of the same register. The DCQ

Read Capture bit immediately self-clears and the result is available in the Mean Slicer Error register.

A software based lookup table (derived empirically in lab conditions) may be used to report a Signal Quality Index (SQI)

number.

Note:

The GPIO needs to be enabled and its direction set as an output via the General Purpose IO Enable reg-

ister (GPIO_EN) and the General Purpose IO Direction register (GPIO_DIR). The GPIO Buffer Type (GPI-

O_BUF) field in the General Purpose IO Buffer Type register (GPIO_BUF) also applies.

Note:

All registers references in this section are in Extended Page 1.

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