LAN8804D datasheet(82/89 Pages) MICROCHIP

82 / 89 page

LAN8804D

DS00003591K-page 82

Section 4.1.1, "LDO Disable"

This section have been modified. Text changed

from:

“The LDO controller is enabled by default. It may

alternatively be disabled via internal register set-

tings. An external source of 1.1V is necessary if the

LDO is disabled.”

to: “The LDO has been defeatured and LDO_O

should be left disconnected. Microchip recom-

mends disabling the LDO output by setting the

active low LDO enable bit in the Analog Control

required for operation.”

Figure 4-1, "Power Connec-

tions"

Figure modified to remove LDO and replace with

1.21V source.

Table 5-1, "MDI/MDI-X Pin

Mapping"

Corrected MDI/MDI-X Pin Mapping names and des-

ignations

Section 5.19.3, "Software

Power-Down Mode"

Under the second bullet entitled “Voltage Regulator

Controller (LDO)” the sub-bullet text has changed

from: “The LDO controller can be disabled by setting

the active low LDO enable bit in the Analog Control

for operation in this case."

to: “The LDO has been defeatured and LDO_O

should be left disconnected. Microchip recommends

disabling the LDO output by setting the active low

LDO enable bit in the Analog Control Register 11.

An external source of 1.21V is required for opera-

tion.”

Section 6.6.2, "Power

Sequence Timing"

• First two paragraphs in this section have been

modified. Text changed from:

“The recommended power-up sequence is to

have the transceiver (VDDAH, VDDAH_x) and

digital I/O (VDDIO, VDDIO_1) voltages power

up before the 1.1V core (VDDCORE,

VDDAL_x, VDDTXL_SERDES) voltage. If the

1.1V core must power up first, the maximum

lead time for the 1.1V core voltage with respect

to the transceiver and digital I/O voltages must

be 200 µs.

There is no power sequence requirement

between transceiver (VDDAH, VDDAH_x) and

digital I/O (VDDIO, VDDIO_1) power rails.”

to: “There is no power sequence requirement

between transceiver (VDDAH, VDDAH_x),

1.1V core (VDDCORE, VDDAL_x, VDDTXL_-

SERDES), and digital I/O (VDDIO, VDDIO_1)

power rails.”

• The following statement has been removed:

“The recommended power-down sequence is

to have the 1.1V core voltage power-down

before powering down the transceiver and dig-

ital I/O voltages.”

TABLE A-1:

REVISION HISTORY (CONTINUED)

Revision

Section/Figure/Entry

Correction

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