LAN8804D datasheet(56/89 Pages) MICROCHIP

56 / 89 page

LAN8804D

DS00003591K-page 56

- Chip soft reset (EP4.9) does not reset the Gigabit PHYs. If needed, the GPHY Hard Macro soft reset must be

used for this.

- GPHY resistor calibration is also run based on the chip hard reset.

• QSGMII hard and soft resets (QSGMII SerDes, extender, and per-port PCS1Gs)

• QSGMII SerDes transmitter and receiver resets

• Port hard and soft resets (all port-specific logic and macros in each port)

- Neither port hard reset (EP5.80) nor soft reset (EP5.81) will reset the GPHY. If needed, the GPHY Macro hard

or soft reset must be used for this.

• Gigabit PHY hard macro hard and soft resets (per port)

The device also provides a RESET_N input pin. This pin must adhere to the timing requirements detailed in Section

6.6.2, "Power Sequence Timing" and Section 6.6.3, "Reset Pin Configuration Strap Timing". Release from reset is based

on the RESET_N input pin transitioning from low to high.

5.20.4

POWER ON READY (POR) WITH OVER/UNDER VOLTAGE PROTECTION

POR monitors three voltages (Refer to Table 6-10 for the exact specification):

• +1.1V Analog Power Supply (on VDDAL_x) set for ~0.8V (typical) - it is assumed that VDDCORE and VDDAL_x

are externally connected, therefore VDD is indirectly monitored.

• +2.5/3.3V Analog Power Supply (on VDDAH_x) set for ~2.1V (typical)

• Variable I/O Power Supply (on VDDIO) set for ~1.5V (typical)

The POR circuits have a “dead zone” between bottom range of valid operational voltage and where POR trips (e.g., -

15%/20%). The Over/Under Voltage Protection enables tightening this range to just under the bottom of the supply

range.

5.21

JTAG

An IEEE 1149.1 compliant TAP Controller supports boundary scan and various test modes.

The device includes an integrated JTAG boundary-scan test port for board-level testing. The interface consists of four

pins (TDO, TDI, TCK and TMS) and includes a state machine, data register array and an instruction register. The JTAG

pins are described in Table 3-6. The JTAG interface conforms to the IEEE Standard 1149.1 - 2001 Standard Test Access

Port (TAP) and Boundary-Scan Architecture.

All input and output data is synchronous to the TCK test clock input. TAP input signals TMS and TDI are clocked into

the test logic on the rising edge of TCK, while the output signal TDO is clocked on the falling edge.

JTAG pins are multiplexed with the GPIO pins. The JTAG functionality is selected when the TESTMODE pin is asserted.

The implemented JTAG instructions and their OP Codes are shown in Table 5-12. JTAG timing information is provided

in Section 6.6.6, "JTAG Timing".

TABLE 5-12:

JTAG OP CODES

INSTRUCTION

OP CODE

CLAMP

4’b0000

EXTEST

4’b0001

(RESERVED)

4’b0010

(RESERVED)

4’b0011

INTEST

4’b0100

SAMPLE_PRELOAD

4’b0101

HIGHZ

4’b0110

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