TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
INTRODUCTION
Preliminary
1-29
Signal Name
Shared Signal
Ball
Type Description – TCC767
GPIO_B[21] / BM[0]
BCLK
M11
I/O
GPIO_B[21] / Boot Mode bit 0 / I2S Interface BCLK.
The status of BM[2:0] is latched at the rising edge of nRESET and
used to determine the system boot mode. Refer to sections
“BOOTING PROCEDURE” and “MEMORY CONTROLLER” for
detailed description on BM[2:0].
GPIO_B[9]
UT_RX
L10
I/O
GPIO_B[9 ] / UART RX Signal
GPIO_B[8]
UT_TX / SD_nCS
L11
I/O
GPIO_B[8] / UARTTX Signal / DDR SDRAM Chip Select
GPIO_B[7]
N11
I/O
GPIO_B[7]
GPIO_B[5]
nCS[3]
M7
I/O
GPIO_B[5] / External Chip Select 3
GPIO_B[4]
nCS[2]
R2
I/O
GPIO_B[4] / External Chip Select 2
GPIO_B[3]
nCS[1]
M3
I/O
GPIO_B[3] / External Chip Select 1
GPIO_B[2]
nCS[0]
N1
I/O
GPIO_B[2] / External Chip Select 0
GPIO_B[1]
SD_nCS / SD_nCLK
P2
I/O
GPIO_B[1] / Chip select for SDRAM / Inverted Clock for DDR
SDRAM.
GPIO_B[0]
SD_CKE
M10
I/O
GPIO_B[0] / SDRAM clock control
GPIO_D[17]
FGPIO[10] / SCL
E12
I/O
GPIO_D[17] / Fast GPIO bit 10 / I2C SCL
GPIO_D[16]
FGPIO[9] / SDA
C14
I/O
GPIO_D[16] / Fast GPIO bit 9 / I2C SDA
GPIO_D[15]
FGPIO[8]
B15
I/O
GPIO_D[15] / Fast GPIO bit 8
ADC Input Pins
ADIN0
F14
AI
General purpose multi-channelADC input 0
ADIN2
G13
AI
General purpose multi-channelADC input 2
ADIN4
E15
AI
General purpose multi-channelADC input 4
Clock Pins
XIN
K12
I
Main Crystal Oscillator Input for PLL. Input voltage must
not exceed VDD_OSC (1.95V max).
XOUT
K11
O
Main Crystal Oscillator Output for PLL
XFILT
G14
AO
PLL filter output
XTIN
L13
I
Sub Crystal Oscillator Input. 32.768kHz is recommended.
Input voltage must not exceed VDD_OSC (1.95V max).
XTOUT
M14
O
Sub Crystal Oscillator Output
XSCI
C2
I
Crystal Oscillator Input for USB 2.0
XSCO
B2
O
Crystal Oscillator Output for USB 2.0
JTAG Interface Pins
TDI
D11
I
JTAG serial data input for ARM940T
TMS
C10
I
JTAG test mode select for ARM940T
TCK
B11
I
JTAG test clock for ARM940T
TDO
A12
I/O
JTAG serial data output for ARM940T. External pull-up resistor
is required to prevent floating during normal operation.
nTRST
D10
I
JTAG reset signal for ARM940T. Active low.
Mode Control Pins
MODE1
C13
I
Mode Setting Input 1. Used for programming internal NOR
flash. Pull-down for normal operation.
PKG
F11
I
Package ID. Pull-up for normal operation.
nRESET
J11
I
System Reset. Active low.
USB 2.0 Interface Pins
DMRS
E2
I/O
USB 1.1 D- signal.
Connect to external series resistor (39Ω±1%).
DPRS
F4
I/O
USB 1.1 D+ signal.
Connect to external series resistor (39Ω±1%).
DM
C3
I/O
USB 2.0 D- signal.
DP
C1
I/O
USB 2.0 D+ signal.
RREF
B4
I
Connect external reference resistor (12.1kΩ±1%) to
ground (VSS_U20).
RPU
D1
I
Connect external pull-up resistor(1.5kΩ±1%) to USB 2.0
analog power (VDDA_U20).
MS & MSPRO Interface Pins
MS_CLK
L2
O
MS/MSPRO Serial protocol Clock signal.
MS_BS
M2
I/O
MS/MSPRO Serial protocol Bus State signal.
MS_D[3]
M1
I/O
MS/MSPRO Data Line [3]
MS_D[2]
L3
I/O
MS/MSPRO Data Line [2]
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