TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
GPIO PORT
Preliminary
7-1
7 GPIO PORT
7.1 Overview
The TCC76x has a lot of general purpose I/Os that can be programmed by setting internal registers. All I/Os are set
to input mode at reset. Except for GPIO_B[29:26] (USB transceiver I/Os), all pins named with GPIO have the
following features.
-
Programmable internal pull-up resistor
-
Programmable drive strength control (4/6/8/12mA) for output mode
-
Programmable I/O direction control
GD A T A
Write
R ead G D A T A
O utput of other
block
GP IO pin
G SEL, G T SEL
0
2
GIOC O N
1
0
1
O utput of test or
other block
C ontrol of test or
other block
C ontrol of other
block
0
2
1
P ull-up resistor
control from
CF G P Ux register
Figure 7.1 GPIO Block Diagram
The I/O mode can be set by the state of GIOCON register.
If a bit of GIOCON register is 1, the corresponding GPIO pin has come to output mode, and if 0, which is the default
state of GIOCON register, the corresponding GPIO pin is set to input mode.
If GPIO pin is set to input mode, GPIO pin’s state can be fed to CPU by reading GDATA register and when output
mode, GPIO pin’s state can be controlled by the state of the corresponding bit of GDATA register.
If GDATA register is read when the mode is output mode, the value that CPU gets is the one that CPU has written
before.
In the TCC76x, there are various kinds of peripherals that generate its own control signals. These peripherals can
occupy the dedicated GPIO pins. This option is controlled by the state of the GSEL and GTSEL register.
If a bit of these GSEL or GTSEL is 1, the corresponding GPIO pin is entered to other function mode, so used by other
peripherals not by GPIO block. The direction control method of GPIO pins in the other function mode is determined
case by case. One of them follows the normal direction control method using GIOCON register, the other method uses
a its own direction control signals.
For drive strength and internal pull-up resistor control, refer to section 12.2 Miscellaneous Register Description.
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