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TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
CPU
Preliminary
3-1
3 CPU
3.1 Overview
The TCC76x has adopted the ARM940T core for controlling system and processing
various kinds of digital signals. It has a Harvard cache architecture with separate 4Kbyte
data and 4Kbytes instruction caches, each with 4-word of line length.
A protection unit allows eight regions of memory to be defined, each with individual
cache and write buffer configurations and access permissions. The cache system is
software configurable to provide highest average of performance or to meet the needs of
real-time systems.
The followings are key features of ARM940T core.
CPU
ARM940T
Cache
4KB for Data / 4KB for Instruction
Operating State
ARM state / THUMB state
Operating Mode
7 different modes (SVC/UND/ABT/FIQ/IRQ/SYS/USR)
Memory Format
Little endian (ARM940T itself supports big-endian type also,
but the memory controller in the TCC76x only support for
little-endian type)
Address Space
32bit of 4Gbyte
Instruction
32bit (in ARM state) / 16bit (in THUMB state)
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