TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
TIMER / COUNTER
Preliminary
6-4
Following figure illustrates the basic behavior of timer / counter.
TCNT
TCO
TCLK
0
nTREQ
CONT= 1, IEN =1 , PWM =0 , TCKSEL= 0, TREF=3
TCK
1
2
TCO
TCO is inverted
TEQU
TCNT
TCO
TCLK
0
nTREQ
CONT =0 , IEN= 1, PWM= 1, TCKSEL=0 , TREF=3 , TMREF= 1
TCK
1
2
3
TMEQU
0
1
2
TEQU
3
4
5
6
Figure 6.2 Timing diagram of timer/counter
Timer/Counter n Counting Register (TCNTn)
0x80000204 + (0x10 * n)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
TCNTn[19:16]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TCNTn[15:0]
TCNTn is increased by 1 at every pulse of selected clock source. TCNTn can be set to
any value by writing to this register. In case of timer 4 and timer 5, it has 20 bits,
otherwise it has 16 bits.
Timer/Counter n Counting Reference Register (TREFn)
0x80000208 + (0x10 * n)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
TREFn[19:16]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TREFn[15:0]
When TCNTn is reached at TREFn and the CON flag of TCFGn register is set to 1, the
TCNTn is cleared to 0 at the next pulse of selected clock source. According to the TCFGn
settings, various kinds of operations may be done. In case of timer 4 and timer 5, it has 20
bit, otherwise it has 16 bit.
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