TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
TIMER / COUNTER
Preliminary
6-8
TC32 Enable / Pre-scale Value Register (TC32EN)
0x80000280
Bit
Name
Default
R/W
Description
31:30
Reserved
0
R
29
LDM1
0
R/W
Re-load counter when the counter value matched with CMP1.
LOADZERO bit below selects the couter load(start) value.
28
LDM0
0
R/W
Re-load counter when the counter value matched with CMP0
LOADZERO bit below selects the couter load(start) value.
27
Reserved
0
R
26
STOPMODE
0
R/W
0 = Free Running Mode, 1 = Stop Mode.
25
LOADZERO
0
R/W
By default, counter starts from LOADVAL. When this bit is enabled
(1), the counter is forced to count from “0” to “LOADVAL – 1”.
24
ENABLE
0
R/W
Counter Enable
23:0
PRESCALE
0x007FFF
R/W
Pre-scale counter load value. The pre-scale counter always runs
from “0” up to PRESCALE. The default value is for 1Hz counter
when ZCLK = XTIN (32.768kHz).
TC32 Load Value Register (TC32LDV)
0x80000284
Bit
Name
Default
R/W
Description
31: 0
LOADVAL
0x00000000 R/W
Counter Load Value.
The counter is restarted whenenver one of the TC32En and TC32LDV is written.
TC32 Match Value 0 Register (TC32CMP0)
0x80000288
Bit
Name
Default
R/W
Description
31: 0
CMP0
0x00000000 R/W
Counter Match Value
TC32 Match Value 1 Register (TC32CMP1)
0x8000028C
Bit
Name
Default
R/W
Description
31: 0
CMP1
0x00000000 R/W
Counter Match Value
TC32 Pre-scale Counter Current Value Register (TC32PCNT)
0x80000290
Bit
Name
Default
R/W
Description
31:24
Reserved
0x00
R
23: 0
PCNT
0x000000
R
Pre-scale counter current value. The AHB system clock must be
three times faster than the frequency of ZCLK to read valid value.
TC32 Main Counter Current Value Register (TC32MCNT)
0x80000294
Bit
Name
Default
R/W
Description
31: 0
MCNT
0x00000000
R
Main counter current value. When RSYNC is enabled, the AHB
system clock must be faster than the frequency calculated below.
(ZCLK frequency) / (PRESCALE + 1) * 3
TC32 Interrupt Control Register (TC32IRQ)
0x80000298
Bit
Name
Default
R/W
Description
31
IRQCLR
0
R/W
Interrupt Clear Control. When this bit is 0, interrupt status bits
(IRQRSTAT) are cleared by reading this register. When this bit is
set, IRQSTAT bits are cleared only if written with non-zero value.
30
RSYNC
0
R/W
Synchronization control for Counter Current Value Registers
(TC32PCNT and TC32MCNT). 0 = Enable, 1 = Disable.
29:24
BITSEL
0x00
R/W
Counter bit selection value for interrupt generation. Any one of the
counter bits {MCNT[31:0], PCNT[23:0]} selected by BITSEL is used
to generate an interrupt.
0x00 ~ 0x17 :
PCNT[0] ~ PCNT[23]
0x18 ~ 0x38:
MCNT[0] ~ MCNT[31]
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