TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
TABLE OF CONTENTS
Preliminary
vii
Figures
Figure 1.1 TCC760 Functional Block Diagram............................................................................ 1-3
Figure 1.2 TCC761 Functional Block Diagram............................................................................ 1-3
Figure 1.3 TCC763 Functional Block Diagram............................................................................ 1-4
Figure 1.4 TCC764 Functional Block Diagram............................................................................ 1-4
Figure 1.5 TCC766 Functional Block Diagram............................................................................ 1-5
Figure 1.6 TCC767 Functional Block Diagram............................................................................ 1-5
Figure 1.7 TCC768 Functional Block Diagram............................................................................ 1-6
Figure 1.8 TCC760 Package Diagram (128-TQFP-1414 / Top View) ................................. 1-37
Figure 1.9 TCC761-E Package Diagram (208-LQFP-2828 / Top View) .............................. 1-38
Figure 1.10 TCC761-Y Package Diagram (208-TBGA-1515 / Bottom View) ...................... 1-39
Figure 1.11 TCC763/TCC764 Package Diagram (144-BGA-1010 / Bottom View) ............. 1-40
Figure 1.12 TCC766 Package Diagram (232-FPBGA-1414 / Bottom View) ....................... 1-41
Figure 1.13 TCC767 Package Diagram (225-FPBGA-1313 / Bottom View) ....................... 1-42
Figure 1.14 TCC768 Package Diagram (144-BGA-1010 / Bottom View)............................ 1-43
Figure 3.1 Little-Endian Addresses of Bytes-Words .............................................................. 3-2
Figure 3.2 4KB Cache Architecture in ARM940T .................................................................. 3-4
Figure 3.3 Asynchronous Clocking Mode .............................................................................. 3-6
Figure 3.4 Switching from FCLK to HCLK in asynchronous mode........................................ 3-6
Figure 4.1 DAI Block Diagram ............................................................................................... 4-2
Figure 4.2 DAI Bus Timing Diagram ...................................................................................... 4-3
Figure 4.3 CDIF Block Diagram............................................................................................. 4-7
Figure 4.4 CDIF Bus Timing Diagram.................................................................................... 4-8
Figure 5.1 Interrupt Controller Block Diagram ....................................................................... 5-1
Figure 6.1 Timer Counter Block Diagram .............................................................................. 6-1
Figure 6.2 Timing diagram of timer/counter........................................................................... 6-4
Figure 6.3 32-bit Counter Block Diagram .............................................................................. 6-7
Figure 7.1 GPIO Block Diagram ............................................................................................ 7-1
Figure 8.1 Clock Generator Block Diagram........................................................................... 8-1
Figure 8.2 Clock Generator Register Signals ........................................................................ 8-4
Figure 9.1 USB Host Controller Block Diagram................................................................... 9-14
Figure 10.1 UART Block Diagram........................................................................................ 10-1
Figure 10.2 Timing Diagram of UART Transmission ........................................................... 10-2
Figure 11.1 GSIO Block Diagram ........................................................................................ 11-1
Figure 11.2 GSIO operation ................................................................................................. 11-5
Figure 12.1 ADC Controller Block Diagram ......................................................................... 12-1
Figure 12.2 Pull-Up and Drive Strength Control .................................................................. 12-6
Figure 13.1 DMA Controller Block Diagram......................................................................... 13-1
Figure 13.2 Relation between Hop and Burst Transfers (If burst size is 4.) ........................ 13-5
Figure 13.3 The Example Of Various Types of Transfer. ..................................................... 13-6
Figure 13.4 Enabled 2Channel Transfer.............................................................................. 13-8
Figure 14.1 LCD controller Block Diagram .......................................................................... 14-1
Figure 14.2 PIN mapping..................................................................................................... 14-1
Figure 14.3 Output Pixel Data Organization(GPIO_A[31:16] = PXDATA[15:0]).................. 14-3
Figure 14.4 STN LCD pixel data organization ..................................................................... 14-5
Figure 14.5 Color STN Pixel Data ....................................................................................... 14-5
Figure 14.6 Dithering operation ........................................................................................... 14-6
Figure 14.7 STN mode timing.............................................................................................. 14-7
Figure 14.8 Monochrome STN LCD(4bits, 1BPP) example ................................................ 14-8
Figure 14.9 TFT LCD pixel data memory organization........................................................ 14-9
Figure 14.10 TFT LCD output pixel data.............................................................................. 14-9
Figure 14.11 TFT LCD(RGB565) example ........................................................................ 14-10
Figure 14.12 TFT mode timing........................................................................................... 14-10
Figure 14.13 NTSC interlace mode timing......................................................................... 14-11
Figure 14.14 PAL interlace mode timing ............................................................................ 14-12
Figure 14.15 Example: NTSC interlace mode timing diagram .......................................... 14-13
Figure 15.1 Memory Controller Block Diagram.................................................................... 15-1
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