IMX95CEC datasheet(16/124 Pages) NXP

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Table 14. 19 x 19 mm FCBGA thermal resistance data

Rating

Board type[1]

Symbol

Value

Unit

Bare die

Lidded

Junction to Ambient

thermal resistance[2]

JESD51-9, 2s2p

RθJA

13.4

12.3

℃/W

Junction-to-Top of package

thermal characterization parameter[2]

JESD51-9, 2s2p

ψJT

0.1

0.4

℃/W

Junction to Case thermal resistance[3]

JESD51-9, 1s

RθJC

0.2

0.6

℃/W

[1] Thermal test board meets JEDEC specification for this package (JESD51-9).

[2] Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is solely for a thermal performance

comparison of one package to another in a standardized specified environment. It is not meant to predict the performance of a package in an application-

specific environment.

[3] Junction-to-Case thermal resistance determined using an isothermal cold plate. Case temperature refers to the package top side surface.

4.1.4 Power architecture

The i.MX power architecture is designed with the expectation that a dedicated PMIC supplies all required power rails,

ensuring compliance with stringent power-up and power-down sequencing requirements. While discrete component-based

implementations are technically viable, they typically lead to increased BOM cost, greater design complexity, and a larger PCB

footprint. In contrast, the proposed PMIC solution is BOM-optimized, minimizes board area by integrating multiple power functions

into a single package, and simplifies system design by providing a validated, production-tested power management solution that

inherently meets the voltage and sequencing specifications of the i.MX platform.

NVCC_BBSM_1P8 must be powered first and stay until the last.

Majority of the digital logic is supplied with two supplies: VDD_ARM and VDD_SOC.

• VDD_ARM is for the CORTEXAMIX.

• VDD_SOC is for the rest of the modules in SoC.

The VDD_SOC has following modes:

• Overdrive mode

• Nominal mode

• Underdrive mode

• Suspend mode

GPIO interfaces functionally only need to operate at 1.8 V. One exception is the SD card interface, which must support both 1.8

V and 3.3 V (for compatibility with legacy 3.3 V SD cards), as well as the “GPIO” pins that may be connected to a EXPI(2x20-pin

Expansion interface) (which for compatibility with components in the ecosystem need to be able to support 3.3 V, while also

needing to support 1.8 V for 1.8 V-optimized designs).

The DRAM controller and PHY have multiple external power supplies:

Table 15. Power supplies of the DRAM controller and PHY

Power supplies

Modules

VDD_SOC

SoC synthesized DRAM controller digital logic

VDD_ANA_0P8/VDD_DDR_0P8

DRAM PLL and PHY digital logic

VDD_ANA_1P8

DRAM PLL and PHY analog circuitry

Table continues on the next page...

NXP Semiconductors

IMX95CEC

i.MX 95 Applications Processors Data Sheet for Commercial Products

IMX95CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 7 April 2026

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