IMX95CEC datasheet(2/124 Pages) NXP

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1 Introduction

i.MX 95 applications processors offer advanced graphics and video cores, powerful vision and machine learning acceleration,

efficient CPU performance plus real-time processing and advanced security with integrated EdgeLock® secure enclave to support

energy-efficient Edge Computing.

i.MX 95 applications processors integrate up to six Arm Cortex®-A55 cores and are the first i.MX devices to support functional

safety with built-in Arm Cortex®-M33 which can be configured as a safety island. Optimizing performance and power efficiency for

Industrial, IoT and Automotive devices, i.MX 95 processors are built with NXP’s innovative Energy Flex architecture.

i.MX 95 applications processors offer a rich set of peripherals targeting automotive, industrial and commercial IoT market

segments. Part of the EdgeVerse™ portfolio of intelligent edge solutions, i.MX 95 family will be offered in Commercial, Industrial,

Extended Industrial and Automotive level qualification and backed by NXP’s product longevity program.

Table 1. Feature summary

Subsystem

Features

Arm Cortex-A55 MPCore platform

• 6x Arm Cortex-A55, up to 2.0 GHz frequency

• Arm v8.2 fully 64-bit capable

• 32 kB L1 instruction cache, 32 kB L1 data cache (per core, parity protected)

• 64 kB L2 cache (per core, ECC protected)

• 512 kB L3 cache (shared across all cores, ECC protected)

Arm Cortex-M7 platform

• 1x Cortex-M7, up to 800 MHz frequency

• Arm v8-M supporting Trustzone-M

• 512 kB TCM (Tightly Coupled Memory), sum of instruction and data

Arm Cortex-M33 platform

• 1x Cortex-M33, up to 333 MHz frequency

• Arm v8-M supporting Trustzone-M

• 16 kB instruction cache + 16 kB data cache (ECC)

• 512 kB TCM, sum of instruction and data

Memory

• 19 x 19 mm package: one x32 LPDDR interface (with inline ECC), operating at

up to 6400MT/s in LPDDR5 mode or 4266 MT/s in LPDDR4X mode.

• 15 x 15 mm package: one x32 LPDDR interface (with inline ECC), operating at

up to 4266 MT/s in LPDDR5 mode or 4000 MT/s in LPDDR4X mode.

• 3x uSDHC (SD3.0, SDIO3.0, eMMC5.1)

• 8x LPI2C

• 8x LPSPI

• 2x I3C

• 1x Octal SPI, including support for SPI NOR and SPI NAND memories

• FlexSPI_FLR

Tightly Coupled Memory

1492 kB total, consisting of:

Table continues on the next page...

NXP Semiconductors

IMX95CEC

i.MX 95 Applications Processors Data Sheet for Commercial Products

IMX95CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 7 April 2026

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