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= 0, SAI_RCR4[FSP] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by

inverting the clock signal (SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.

The DSE[5:0] = 001111 and FSEL1[1:0] = 11 are required drive settings to meet the timing.

The SAI4 pins muxed with ENET2 and the SAI4 pins muxed with XSPI1 are mutually exclusive. It does not support a use case

where some SAI4 pins are connected to ENET2 and other SAI4 pins are simultaneously connected to XSPI1.

SAI5 is supported entirely on SD3 or entirely on XSPI1 (but not multiplexed across both XSPI1 and SD3 pins). SAI5 is also

supported with some pins on SD3 and others on XSPI1, as long as the non-data signals (SYNCs and/or BCLKs) are on the one

interface (SD3 or XSPI1), and all TX_DATA pins are on the one interface (SD3 or XSPI1), and all RX_DATA pins are on the one

interface (SD3 or XSPI1).

SAI2 is supported entirely on ENET pins (at up to maximum supported speeds). However, the SAI2 on XSPI1 pins are limited

to no more than 25 MHz – the faster 50 MHz Controller Tx and 66.67 MHz Target Rx modes are supported by the SAI2 only on

ENET2 pins.

4.9.1.1 SAI/I2S Controller mode timing (50 MHz)

To achieve 50 MHz for BCLK operation, clock must be set in feedback mode and TCR2[BCI] = 1 must be configured to enable it

for the transmitter.

Input timing assumes an input signal slew rate of 3 ns (20%/80%).

Output timing valid for maximum external load CL = 25 pF, which is assumed to be a 10-pF load at the end of a 50

ohm, unterminated, 5-inch microstrip trace on standard FR4 (3.3 pF/inch), (25-pF total with margin). For best signal integrity,

the series resistance in the transmission line should be equal to the selected RDSON of the I/O pad output driver.

Table 47. SAI/I2S Controller mode timing (50 MHz)

Symbol

Description

Min

Typ

Max

Unit

Condition

Spec

Number

SAI_MCLK cycle

time

—

SAI_MCLK pulse

width high/low

40%

—

60%

MCLK

period

—

SAI_BCLK cycle

time

—

SAI_BCLK pulse

width high/low

40%

—

60%

BCLK

period

—

SAI_BCLK to

SAI_FS output valid

—

SAI_BCLK to

SAI_FS output

invalid

-2

—

SAI_BCLK to

SAI_TXD valid

—

SAI_BCLK to

SAI_TXD invalid

-2

—

SAI_RXD/SAI_FS

input setup before

SAI_BCLK

—

Table continues on the next page...

NXP Semiconductors

IMX95CEC

i.MX 95 Applications Processors Data Sheet for Commercial Products

IMX95CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 7 April 2026

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