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Table 44. SWD timing parameters...continued

Symbol

Description

Min

Typ

Max

Unit

Condition

Spec

Number

Input data setup time 5

—

Input data hold time 5

—

Output data valid

time

—

Output high

impedance time

—

Output data invalid

time

—

Input timing assumes an input signal slew rate of 3 ns (20%/80%).

Timing valid for maximum external load CL = 25 pF, which is assumed to be a 10 pF load at the end of a 50 Ω , unterminated,

5-inch microstrip trace on standard FR4 (3.3 pF/inch), (25 pF total with margin). For best signal integrity, the series resistance in

the transmission line can be equal to the selected RDSON of the I/O pad output.

Following figure depicts the SWD timing.

SWD_CLK (input)

SWD_DIO (input)

SWD_DIO (output)

Figure 14. SWD timing

4.7.4 DDR SDRAM–specific parameters (LPDDR5/LPDDR4X)

The i.MX95 Family of processors have been designed and tested to work with JEDEC JESD209—compliant LPDDR5/

LPDDR4X memory.

• JEDEC LPDDR4X Specification JESD209-4C, November 2019

• JEDEC LPDDR5 Specification JESD209-5A, January 2020

Timing diagrams and tolerances required to work with these memories are specified in the respective documents and are not

reprinted here.

NXP Semiconductors

IMX95CEC

i.MX 95 Applications Processors Data Sheet for Commercial Products

IMX95CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 7 April 2026

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