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IMX95CEC Datasheet(PDF) 9 Page - NXP Semiconductors |
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IMX95CEC Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 124 page ![]() | NXP | Confidential 1 Application Domain Real-Time Domain Memory x32 LPDDR5/LPDDR4X (Inline ECC & Encryption) MCU Arm® Cortex-M7 FPU 512kB TCM (ECC) NVIC 32kB + 32kB I / D Cache MPU Low-Power Real Time Domain System Control EdgeLock® Secure Enclave Watchdog, Periodic Timer Connectivity & I/O Temperature Sensor Timer/PWM x2, Timer x2 DMA System/Safety Manager Arm Cortex -M33 FPU 512kB TCM/OCRAM (ECC) NVIC 16kB + 16kB Cache MPU UART/USART x2, SPI x2 I2C x2, CAN -FD 8-ch PDM Mic Input 2-lane I2S TDM Tx/Rx Medium Quality Sound Output Flex Domain Connectivity & I/O UART/USART x6 I2C x6 4x CAN-FD 2x 32-bit FlexIO ADC (8-channel, 12 -bit) System Control DMA x2 Timer/PWM Secure JTAG Watchdog x3, Periodic Timer ML & Multimedia Arm® Mali™ 3D GPU + 2D GPU 2x MIPI-CSI 4-lane (1 mux w/DSI) 15-lane I2S TDM Tx/Rx SPDIF Tx/Rx 1x MIPI-DSI 4-lane (w/PHY) High Speed I/O 3x SD / SDIO3.0 / eMMC5.1 Octal SPI FLASH (inline crypto) 1492kB OCRAM (ECC) 4K Video Processing Unit Image Signal Processor XSPI responder eIQ® Neutron N3 -1024S NPU 2x 4-lane or 1x 8 -lane LVDS Multi-Core CPU Coherent 512kB L3 Cache (ECC) USB 3.0 + USB 2.0 2x 1 GbE (w/TSN) 2x PCIe® Gen 3.0 x12 10 GbE (w/TSN)2 Crypto Tamper Detection Secure Clock Secure Boot eFuse Key Storage Random Number Arm® Cortex-A55 FPU NEON 64kB L2 Cache 32kB i-Cache 32kB d-Cache SPI x6 x6 Figure 3. i.MX 95 system block diagram Note: 1. Above figure represents 19 x 19 mm package. 2. 15 x 15 mm package supports 1 PCIe and does not have 10 GbE. 3. Some modules shown in this block diagram are not offered on all derivatives. 3 Special Signal Considerations Table 3 lists special signal considerations for the i.MX 95 processors. The signal names are listed in alphabetical order. NXP Semiconductors IMX95CEC i.MX 95 Applications Processors Data Sheet for Commercial Products IMX95CEC All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 8 — 7 April 2026 Document feedback 9 / 124 |
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