IMX95CEC datasheet(36/124 Pages) NXP

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4.3 PLL electrical characteristics

Following sections introduce the Fractional-N (FracN) Phase-Locked Loops (PLL) and Low Noise PLL electrical

characteristics.

4.3.1 Fracn PLL

Table 34. Fracn PLL

Symbol

Description

Min

Typ

Max

Unit

Condition

Spec

Number

TLock

PLL lock time

100

µS

—

Fout

Output Clock

Frequency [1]

9.8M

—

2.5G

—

FPLL_MOD

SSCG modulation

frequency

kHz

@40MHz and 50MHz

ref clk

—

ΔFPLL_MOD

SSCG modulation

depth

-4*Fref*pf

—

Down Spread

—

[1] This specification is PLL input reference clock frequency after pre-divider.

4.3.2 Low Noise PLL

Table 35. Low Noise PLL

Symbol

Description

Min

Typ

Max

Unit

Condition

Spec

Number

TLock

PLL lock time

—

100

µs

—

FPLL_MOD

SSCG modulation

frequency

—

KHz

at Fref_pfd < 40 MHz

—

ΔFPLL_MOD

SSCG modulation

depth

-4*Fref*pf

—

Down Spread

—

4.4 I/O DC parameters

This section includes the DC parameters of the following I/O types:

• General Purpose I/O (GPIO)

• Double Data Rate I/O (DDR) for LPDDR5 and LPDDR4X modes

• LVDS I/O

4.4.1 General purpose I/O (GPIO) DC parameters

The following tables show the DC parameters for GPIO pads. The parameters are guaranteed per the operating ranges

table, unless otherwise noted.

NXP Semiconductors

IMX95CEC

i.MX 95 Applications Processors Data Sheet for Commercial Products

IMX95CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 7 April 2026

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