SH7124 datasheet(153/782 Pages) RENESAS

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Section 7

User Break Controller (UBC)

Rev. 3.00

Sep. 27, 2007

Page 133 of 758

REJ09B0243-0300

7.2.14

Branch Destination Register (BRDR)

BRDR is a 32-bit read-only register. BRDR stores bits 27 to 0 in the address of the branch

destination instruction. BRDR has the flag bit that is set to 1 when a branch occurs. This flag bit is

cleared to 0 by a power-on reset or manual reset when BRDR is read or the setting to enable PC

trace is made. Other bits are not initialized by a power-on reset. The eight BRDR registers have a

queue structure and a stored register is shifted at every branch.

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

987654321

0000

RRRRRRRRRRRRRRRR

----------------

RRRRRRRRRRRRRRRR

DVF

BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16

BDA15 BDA14 BDA13 BDA12 BDA11 BDA10

BDA9

BDA8

BDA7

BDA6

BDA5

BDA4

BDA3

BDA2

BDA1

BDA0

Bit

Bit Name

Initial

Value

R/W

Description

DVF

BRDR Valid Flag

Indicates whether a branch destination address is

stored. This flag bit is set to 1 when a branch occurs.

This flag is cleared to 0 when BRDR is read, the

setting to enable PC trace is made, or BRDR is

initialized by a power-on reset.

0: The value of BRDR register is invalid

1: The value of BRDR register is valid

30 to 28



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

27 to 0

BDA27 to

BDA0

Undefined R

Branch Destination Address

Store bits 27 to 0 of the branch destination address.

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