SH7124 datasheet(156/782 Pages) RENESAS

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Section 7

User Break Controller (UBC)

Rev. 3.00

Sep. 27, 2007

Page 136 of 758

REJ09B0243-0300

Table 7.2

Data Access Cycle Addresses and Operand Size Comparison Conditions

Access Size

Address Compared

Longword

Compares break address register bits 31 to 2 to address bus bits 31 to 2

Word

Compares break address register bits 31 to 1 to address bus bits 31 to 1

Byte

Compares break address register bits 31 to 0 to address bus bits 31 to 0

This means that when address H'00001003 is set in the break address register (BARA or

BARB), for example, the bus cycle in which the break condition is satisfied is as follows

(where other conditions are met).

Longword access at H'00001000

Word access at H'00001002

Byte access at H'00001003

3. When the data value is included in the break conditions:

When the data value is included in the break conditions, either longword, word, or byte is

specified as the operand size of the break bus cycle register (BBRA or BBRB). When data

values are included in break conditions, a break is generated when the address conditions and

data conditions both match. To specify byte data for this case, set the same data in two bytes at

bits 15 to 8 and bits 7 to 0 of the break data register (BDRA or BDRB) and break data mask

and BDMRA or BDMRB are ignored.

4. If the L bus is selected, a break occurs on ending execution of the instruction that matches the

break condition, and immediately before the next instruction is executed. However, when data

is also specified as the break condition, the break may occur on ending execution of the

instruction following the instruction that matches the break condition. If the I bus is selected,

the instruction at which the break will occur cannot be determined. When this kind of break

occurs at a delayed branch instruction or its delay slot, the break may not actually take place

until the first instruction at the branch destination.

SH7124 Datasheet(PDF) 156 Page - Renesas Technology Corp