SH7124 datasheet(164/782 Pages) RENESAS

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Section 7

User Break Controller (UBC)

Rev. 3.00

Sep. 27, 2007

Page 144 of 758

REJ09B0243-0300

7.4

Usage Notes

1. The CPU can read from or write to the UBC registers via the I bus. Accordingly, during the

period from executing an instruction to rewrite the UBC register till the new value is actually

rewritten, the desired break may not occur. In order to know the timing when the UBC register

is changed, read from the last written register. Instructions after then are valid for the newly

written register value.

2. UBC cannot monitor access to the L bus and I bus in the same channel.

3. Note on specification of sequential break:

A condition match occurs when a B-channel match occurs in a bus cycle after an A-channel

match occurs in another bus cycle in sequential break setting. Therefore, no break occurs even

if a bus cycle, in which an A-channel match and a channel B match occur simultaneously, is

set.

4. When a user break and another exception occur at the same instruction, which has higher

priority is determined according to the priority levels defined in table 5.1 in section 5,

Exception Handling. If an exception with higher priority occurs, the user break is not

generated.

 Pre-execution break has the highest priority.

 When a post-execution break or data access break occurs simultaneously with a re-

execution-type exception (including pre-execution break) that has higher priority, the re-

execution-type exception is accepted, and the condition match flag is not set (see the

exception in the following note). The break will occur and the condition match flag will be

set only after the exception source of the re-execution-type exception has been cleared by

the exception handling routine and re-execution of the same instruction has ended.

 When a post-execution break or data access break occurs simultaneously with a

completion-type exception (TRAPA) that has higher priority, though a break does not

occur, the condition match flag is set.

5. Note the following exception for the above note.

If a post-execution break or data access break is satisfied by an instruction that generates a

CPU address error by data access, the CPU address error is given priority to the break. Note

that the UBC condition match flag is set in this case.

6. Note the following when a break occurs in a delay slot.

If a pre-execution break is set at the delay slot instruction of the RTE instruction, the break

does not occur until the branch destination of the RTE instruction.

7. User breaks are disabled during UBC module standby mode. Do not read from or write to the

UBC registers during UBC module standby mode; the values are not guaranteed.

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