SLRC400 datasheet(89/130 Pages) PHILIPS

89 / 130 page

Philips Semiconductors

Product Specification Rev. 2.0 November 2001

•CODE Reader IC

SL RC400

Preliminary

RECEIVER CIRCUITRY

14.1

General

The SL RC400 employs an integrated quadrature-demodulation circuit which extracts the sub-carrier signal

from the 13.56 MHz ASK-modulated signal applied to pin RX. The quadrature-demodulator uses two

different clocks, Q- and

I-clock, with a phase shift of 90° between them. Both resulting subcarrier signals are

amplified, filtered and forwarded to the correlation circuitry. The correlation results are evaluated, digitised

and passed to the digital circuitry.

For all processing units various adjustments can be made to obtain optimum performance.

14.2

Block Diagram

Figure 14-1 shows the block diagram of the receiver circuitry. The receiving process includes several steps.

First the quadrature demodulation of the carrier signal of 13.56 MHz is done. To achieve an optimum in

performance an automatic clock Q calibration is recommended (see 14.3.1). The demodulated signal is

amplified by an adjustable amplifier. A correlation circuit calculates the degree of similarity between the

expected and the received signal. The bit phase register allows to align the position of the correlation

intervals with the bit grid of the received signal. In the evaluation and digitizer circuitry the valid bits are

detected and the digital results are send to the FIFO register. Several tuning steps in this circuit are possible.

The user may observe the signal on its way through the receiver as shown in the block diagram above. One

signal at a time may be routed to pin AUX using the TestAnaSelect-Register as described in 18.3.

13.56 MHz

Demodulator

I to Q

Conversion

Q-clock

I-clock

Correlation

Circuitry

VRxFoll

VRxFollQ

VRxAmp

VRxAmpQ

VCorrN

VCorrDQ

VCorrD

VCorrNQ

VEvalL

VEvalR

TestAna

OutSel

Gain[1:0]

Evaluation and Digitizer

Circuitry

s_valid

s_data

s_coll

s_clock

BitPhase[7:0]

MinLevel[3:0]

CollLevel[3:0]

ClockQCalib

ClockQDelay[4:0]

ClockQ180°

clock

RcvClkSel

RxWait[7:0]

Figure 14-1: Block Diagram of Receiver Circuitry

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