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SLRC400 Datasheet(PDF) 12 Page - NXP Semiconductors |
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SLRC400 Datasheet(HTML) 12 Page - NXP Semiconductors |
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12 / 130 page ![]() Philips Semiconductors Product Specification Rev. 2.0 November 2001 I •CODE Reader IC SL RC400 12 Preliminary 4 PARALLEL INTERFACE 4.1 Overview of Supported µ-Processor Interfaces The SL RC400 supports direct interfacing of various µ-Processor. Alternatively the Enhanced Parallel Port (EPP) of personal computers can be connected directly. The following table shows the parallel interface signals supported by the SL RC400: Bus Control Signals Bus Separated Address and Data Bus Multiplexed Address and Data Bus control NRD, NWR, NCS NRD, NWR, NCS, ALE address A0, A1, A2 AD0, AD1, AD2, (AD3, AD4, AD5) Separated Read and Write Strobes data D0 … D7 AD0 … AD7 control R/NW, NDS, NCS R/NW, NDS, NCS, AS address A0, A1, A2 AD0, AD1, AD2, (AD3, AD4, AD5) Common Read and Write Strobe data D0 … D7 AD0 … AD7 control nWrite, nDStrb, NCS, nAStrb, nWait address AD0, AD1, AD2, (AD3, AD4, AD5) Common Read and Write Strobe with Handshake (EPP) data - AD0 … AD7 Table 4-1: Supported µ-Processor Interface Signals 4.2 Automatic µ-Processor Interface Type Detection After each Power-On or Hard Reset, the SL RC400 also resets its parallel µ-Processor interface mode and checks the current µ-Processor interface type. The SL RC400 identifies the µ-Processor interface by means of the logic levels on the control pins after the Reset Phase. This is done by a combination of fixed pin connections (see below) and a dedicated initialisation routine (see 11.4). |
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