21150 datasheet(69/164 Pages) INTEL

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21150

Preliminary Datasheet

The prefetchable memory address range has a granularity and alignment of 1MB. The maximum

memory address range is 4GB when 32-bit addressing is used, and 2

64 bytes when 64-bit

addressing is used.

The prefetchable memory address range is defined by a 16-bit prefetchable memory base address

offset 28h. The top 12 bits of each of these registers correspond to bits <31:20> of the memory

address. The low 4 bits are hardwired to 1h, indicating 64-bit address support. The low 20 bits of

the prefetchable memory base address are assumed to be 0 0000h, which results in a natural

alignment to a 1MB boundary. The low 20 bits of the prefetchable memory limit address are

assumed to be F FFFFh, which results in an alignment to the top of a 1MB block.

Note:

The initial state of the prefetchable memory base address register is 0000 0000h. The initial state of

the prefetchable memory limit address register is 000F FFFFh. Note that the initial states of these

registers define a prefetchable memory range at the bottom 1MB block of memory. Write these

registers with their appropriate values before setting either the memory enable bit or the master

enable bit in the command register in configuration space.

To turn off the prefetchable memory address range, write the prefetchable memory base address

base value must be greater than the entire limit value, meaning that the upper 32 bits must be

considered. Therefore, to disable the address range, the upper 32 bits registers can both be set to the

same value, while the lower base register is set greater than the lower limit register; otherwise, the

upper 32-bit base must be greater than the upper 32-bit limit.

5.3.3

Prefetchable Memory 64-Bit Addressing Registers

The 21150 supports 64-bit memory address decoding for forwarding of dual address memory

transactions. The dual address cycle is used to support 64-bit addressing. The first address phase of

a dual address transaction contains the low 32 address bits, and the second address phase contains

the high 32 address bits. During a dual address cycle transaction, the upper 32 bits must never be

0—use the single address cycle commands for transactions addressing the first 4GB of memory

space.

The 21150 implements the prefetchable memory base address upper 32 bits register and the

prefetchable memory limit address upper 32 bits register to define a prefetchable memory address

range greater than 4GB. The prefetchable address space can then be defined in three different

ways:

• Residing entirely in the first 4GB of memory

• Residing entirely above the first 4GB of memory

• Crossing the first 4GB memory boundary

If the prefetchable memory space on the secondary interface resides entirely in the first 4GB of

memory, both upper 32 bits registers must be set to 0. The 21150 ignores all dual address cycle

transactions initiated on the primary interface and forwards all dual address transactions initiated

on the secondary interface upstream.

If the secondary interface prefetchable memory space resides entirely above the first 4GB of

memory, both the prefetchable memory base address upper 32 bits register and the prefetchable

memory limit address upper 32 bits register must be initialized to nonzero values. The 21150

ignores all single address memory transactions initiated on the primary interface and forwards all

single address memory transactions initiated on the secondary interface upstream (unless they fall

21150 Datasheet(PDF) 69 Page - Intel Corporation

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