21150 datasheet(37/164 Pages) INTEL

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21150

Preliminary Datasheet

The 21150 responds only to dual address transactions that use the following transaction command

codes:

• Memory write

• Memory write and invalidate

• Memory read

• Memory read line

• Memory read multiple

Use of other transaction codes may result in a master abort.

Any memory transactions addressing the first 4GB space should use a single address phase; that is,

the high 32 bits of a dual address transaction should never be 0.

4.3

Device Select (DEVSEL#) Generation

The 21150 always performs positive address decoding when accepting transactions on either the

primary or secondary buses. The 21150 never subtractively decodes. Medium DEVSEL# timing is

used on both interfaces.

4.4

Data Phase

The address phase or phases of a PCI transaction are followed by one or more data phases. A data

phase is completed when IRDY# and either TRDY# or STOP# are asserted. A transfer of data

occurs only when both IRDY# and TRDY# are asserted during the same PCI clock cycle. The last

data phase of a transaction is indicated when FRAME# is deasserted and both TRDY# and IRDY#

are asserted, or when IRDY# and STOP# are asserted. See Section 4.8 for further discussion of

transaction termination.

Depending on the command type, the 21150 can support multiple data phase PCI transactions. For

a detailed description of how the 21150 imposes disconnect boundaries, see Section 4.5.4 for a

description of write address boundaries and Section 4.6.3 for a description of read address

boundaries.

4.5

Write Transactions

Write transactions are treated as either posted write or delayed write transactions. Table 16 shows

the method of forwarding used for each type of write operation.

Table 16. Write Transaction Forwarding

Type of Transaction

Type of Forwarding

Memory write

Posted

Memory write and invalidate

Posted

I/O write

Delayed

Type 1 configuration write

Delayed

21150 Datasheet(PDF) 37 Page - Intel Corporation

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