21150 datasheet(21/164 Pages) INTEL

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21150

Preliminary Datasheet

2.3

Secondary Bus Arbitration Signals

Table 6 describes the secondary bus arbitration signals.

s_lock_l

STS

Secondary PCI interface LOCK#. Signal s_lock_l is

deasserted during the first address phase of a transaction and

is asserted one clock cycle later by the 21150 when it is

propagating a locked transaction downstream. The 21150

does not propagate locked transactions upstream. The 21150

continues to assert s_lock_l until the address phase of the

next locked transaction, or until the lock is released. When the

lock is released, s_lock_l is driven to a deasserted state for

one cycle and then is sustained by an external pull-up resistor.

s_perr_l

STS

Secondary PCI interface PERR#. Signal s_perr_l is asserted

when a data parity error is detected for data received on the

secondary interface. The timing of s_perr_l corresponds to

s_par driven one cycle earlier and s_ad driven two cycles

earlier. Signal s_perr_l is asserted by the target during write

transactions, and by the initiator during read transactions.

When the secondary bus is idle, s_perr_l is driven to a

deasserted state for one cycle and then is sustained by an

external pull-up resistor.

s_serr_l

Secondary PCI interface SERR#. Signal s_serr_l can be

driven low by any device except the 21150 on the secondary

bus to indicate a system error condition. The 21150 samples

s_serr_l as an input and conditionally forwards it to the primary

bus on p_serr_l. The 21150 does not drive s_serr_l. Signal

s_serr_l is pulled up through an external resistor.

Table 5.

Secondary PCI Bus Interface Signals (Sheet 3 of 3)

Signal Name

Type

Description

Table 6.

Secondary PCI Bus Interface Signals (Sheet 1 of 2)

Signal Name

Type

Description

s_req_l<8:0>

Secondary PCI interface REQ#s. The 21150 accepts nine

request inputs, s_req_l<8:0>, into its secondary bus arbiter.

The 21150 request input to the arbiter is an internal signal.

Each request input can be programmed to be in either a high

priority rotating group or a low priority rotating group. An

asserted level on an s_req_l pin indicates that the

corresponding master wants to initiate a transaction on the

secondary PCI bus. If the internal arbiter is disabled (s_cfn_l

tied high), s_req_l<0> is reconfigured to be an external

secondary grant input for the 21150. In this case, an asserted

level on s_req_l<0> indicates that the 21150 can start a

transaction on the secondary PCI bus if the bus is idle.

s_gnt_l<8:0>

Secondary PCI interface GNT#s. The 21150 secondary bus

arbiter can assert one of nine secondary bus grant outputs,

s_gnt_l<8:0>, to indicate that an initiator can start a

transaction on the secondary bus if the bus is idle. The

21150’s secondary bus grant is an internal signal. A

programmable 2-level rotating priority algorithm is used. If the

internal arbiter is disabled (s_cfn_l tied high), s_gnt_l<0> is

reconfigured to be an external secondary bus request output

for the 21150. The 21150 asserts this signal whenever it wants

to start a transaction on the secondary bus.

21150 Datasheet(PDF) 21 Page - Intel Corporation

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