21150 datasheet(49/164 Pages) INTEL

49 / 164 page

21150

Preliminary Datasheet

When the master repeats the transaction and starts transferring prefetchable read data from 21150

data buffers while the read transaction on the target bus is still in progress and before a read

boundary is reached on the target bus, the read transaction starts operating in flow-through mode.

Because data is flowing through the data buffers from the target to the initiator, long read bursts can

then be sustained. In this case, the read transaction is allowed to continue until the initiator

terminates the transaction, or until an aligned 4KB address boundary is reached, or until the buffer

fills, whichever comes first. When the buffer empties, the 21150 reflects the stalled condition to the

initiator by deasserting TRDY# until more read data is available; otherwise, the 21150 does not

insert any target wait states. When the initiator terminates the transaction, the deassertion of

FRAME# on the initiator bus is forwarded to the target bus. Any remaining read data is discarded.

Figure 11 shows a flow-through prefetchable read transaction.

Figure 10. Prefetchable Delayed Read Transaction

73%

LJ-04847.AI4

p_frame_l

p_cbe_l

p_ad

p_irdy_l

p_devsel_l

p_trdy_l

p_stop_l

s_frame_l

s_cbe_l

s_ad

s_irdy_l

s_devsel_l

s_trdy_l

s_stop_l

p_clk

Cycle

CY0

< 15ns >

CY1

CY2

CY3

CY4

CY5

CY6

CY7

CY8

CY10

CY9

CY11

CY12

CY13

CY14

CY15

CY16

CY17

CY18

CY19

CY20

CY21

s_clk

Addr

Byte Enables

Addr

Data

21150 Datasheet(PDF) 49 Page - Intel Corporation

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