21150 datasheet(64/164 Pages) INTEL

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21150

Preliminary Datasheet

Caution:

If any 21150 configuration state affecting I/O transaction forwarding is changed by a configuration

write operation on the primary bus at the same time that I/O transactions are ongoing on the

secondary bus, the 21150 response to the secondary bus I/O transactions is not predictable.

Configure the I/O base and limit address registers, ISA enable bit, VGA mode bit, and VGA snoop

bit before setting the I/O enable and master enable bits, and change them subsequently only when

the primary and secondary PCI buses are idle.

5.2.1

I/O Base and Limit Address Registers

The 21150 implements one set of I/O base and limit address registers in configuration space that

define an I/O address range for downstream forwarding. The 21150 supports 32-bit I/O addressing,

which allows I/O addresses downstream of the 21150 to be mapped anywhere in a 4GB I/O address

space.

I/O transactions with addresses that fall inside the range defined by the I/O base and limit registers

are forwarded downstream from the primary PCI bus to the secondary PCI bus. I/O transactions

with addresses that fall outside this range are forwarded upstream from the secondary PCI bus to

the primary PCI bus.

The I/O range can be turned off by setting the I/O base address to a value greater than that of the

I/O limit address. When the I/O range is turned off, all I/O transactions are forwarded upstream,

and no I/O transactions are forwarded downstream.

Figure 15 illustrates transaction forwarding within and outside the I/O address range.

The 21150 I/O range has a minimum granularity of 4KB and is aligned on a 4KB boundary. The

maximum I/O range is 4GB in size.

The I/O base register consists of an 8-bit field at configuration address 1Ch, and a 16-bit field at

address 30h. The top 4 bits of the 8-bit field define bits <15:12> of the I/O base address. The

bottom 4 bits read only as 1h to indicate that the 21150 supports 32-bit I/O addressing. Bits <11:0>

of the base address are assumed to be 0, which naturally aligns the base address to a 4KB boundary.

Figure 15. I/O Transaction Forwarding Using Base and Limit Addresses

LJ-04636.AI4

I/O Limit

Primary

Interface

Secondary

Interface

4KB

Multiple

I/O Base

I/O Address Space

21150 Datasheet(PDF) 64 Page - Intel Corporation