21150 datasheet(47/164 Pages) INTEL

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21150

Preliminary Datasheet

4.6.5

Delayed Read Completion with Target

When the delayed read request reaches the head of the delayed transaction queue, and all

previously queued posted write transactions have been delivered, the 21150 arbitrates for the target

bus and initiates the read transaction, using the exact read address and read command captured

from the initiator during the initial delayed read request. If the read transaction is a nonprefetchable

read, the 21150 drives the captured byte enable bits during the next cycle. If the transaction is a

prefetchable read transaction, it drives all byte enable bits to 0 for all data phases. If the 21150

receives a target retry in response to the read transaction on the target bus, it continues to repeat the

read transaction until at least one data transfer is completed, or until an error condition is

encountered. If the transaction is terminated via normal master termination or target disconnect

after at least one data transfer has been completed, the 21150 does not initiate any further attempts

to read more data.

If the 21150 is unable to obtain read data from the target after 2

24 attempts, the 21150 ceases further

read attempts and returns a target abort to the initiator. The delayed transaction is removed from the

delayed transaction queue. The 21150 also asserts p_serr_l if the primary SERR# enable bit is set

in the command register. See Section 7.4 for information on the assertion of p_serr_l.

Once the 21150 receives DEVSEL# and TRDY# from the target, it transfers the data read to the

opposite direction read data queue, pointing toward the opposite interface, before terminating the

transaction. For example, read data in response to a downstream read transaction initiated on the

primary bus is placed in the upstream read data queue. The 21150 can accept 1 Dword of read data

each PCI clock cycle; that is, no master wait states are inserted. The number of Dwords transferred

during a delayed read transaction depends on the conditions given in Table 19 (assuming no

disconnect is received from the target).

4.6.6

Delayed Read Completion on Initiator Bus

When the transaction has been completed on the target bus, and the delayed read data is at the head

of the read data queue, and all ordering constraints with posted write transactions have been

satisfied, the 21150 transfers the data to the initiator when the initiator repeats the transaction. For

memory read transactions, the 21150 aliases the memory read, memory read line, and memory read

multiple bus commands when matching the bus command of the transaction to the bus command in

the delayed transaction queue.The 21150 returns a target disconnect along with the transfer of the

last Dword of read data to the initiator. If the initiator terminates the transaction before all read data

has been transferred, the remaining read data left in data buffers is discarded.

Figure 9 shows a nonprefetchable delayed read transaction.

21150 Datasheet(PDF) 47 Page - Intel Corporation