21150 datasheet(57/164 Pages) INTEL

57 / 164 page

21150

Preliminary Datasheet

When a master abort is received in response to a posted write transaction, the 21150 discards the

posted write data and makes no more attempts to deliver the data. The 21150 sets the received

master abort bit in the status register when the master abort is received on the primary bus, or it sets

the received master abort bit in the secondary status register when the master abort is received on

the secondary interface.

When a master abort is detected in response to a posted write transaction, and the master abort

mode bit is set, the 21150 also asserts p_serr_l if enabled by the SERR# enable bit in the command

posted write transactions (that is, master abort mode = 1; SERR# enable bit = 1; and p_serr_l

disable bit for master aborts = 0.)

Note:

When the 21150 performs a Type 1 to special cycle translation, a master abort is the expected

termination for the special cycle on the target bus. In this case, the master abort received bit is not

set, and the Type 1 configuration transaction is disconnected after the first data phase.

Figure 13. Delayed Write Transaction Terminated with Master Abort

91% LJ-04849.AI4

p_frame_l

p_cbe_l

p_ad

p_irdy_l

p_devsel_l

p_trdy_l

p_stop_l

s_frame_l

s_cbe_l

s_ad

s_irdy_l

s_devsel_l

s_trdy_l

s_stop_l

p_clk

s_clk

Cycle

CY0

< 15ns >

CY1

CY2

CY3

CY4

CY5

CY6

CY7

CY8

CY10

CY9

CY11

CY12

CY13

CY14

CY15

CY16

Addr

Data

Addr

Data

Byte Enables

21150 Datasheet(PDF) 57 Page - Intel Corporation

21150 Datasheet(HTML) 57 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL