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21150 Datasheet(PDF) 13 Page - Intel Corporation |
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21150 Datasheet(HTML) 13 Page - Intel Corporation |
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13 / 164 page ![]() 21150 Preliminary Datasheet 5 1.2 Data Path The data path consists of a primary-to-secondary data path for transactions and data flowing in the downstream direction and a secondary-to-primary data path for transactions and data flowing in the upstream direction. Both data paths have the following queues: • Posted write queue • Delayed transaction queue • Read data queue To prevent deadlocks and to maintain data coherency, a set of ordering rules is imposed on the forwarding of posted and delayed transactions across the 21150. The queue structure, along with the order in which the transactions in the queues are initiated and completed, supports these ordering requirements. Section 6.0 describes the 21150 ordering rules in detail. See Section 4.0 for a detailed description of 21150 PCI bus operation. Figure 4 shows the 21150 data path for the downstream direction, and the following sections describe the data path queues. Secondary-to-Primary Data Path Data path for data received on the secondary interface and driven on the primary interface. This block is used for write transactions initiated on the secondary PCI bus and for returning read data for read transactions initiated on the primary PCI bus. This block contains logic to store and, for posted write transactions, to increment the address of the current transaction. This block also performs bus command and configuration address format translations Configuration Registers Configuration space registers and corresponding control logic. These registers are accessible from the primary interface only. Secondary Bus Arbiter Control Logic for secondary bus arbitration. This block receives s_req_l<8:0>, as well as the 21150 secondary bus request, and drives one of the s_gnt_l<8:0> lines or the 21150 secondary bus grant. Table 1. 21150 Functional Blocks (Sheet 2 of 2) Figure 4. 21150 Downstream Data Path LJ-04634.AI4 s_ad Delayed Transaction Queue Address Control Delayed Read Data Queue Posted Write Data Queue |
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