ADG714/ADG715

Data Sheet

Rev. E | Page 8 of 21

Parameter

Limit at TMIN, TMAX

Unit

Conditions/Comments

Cb

400

pF max

Capacitive load for each bus line

tSP3

50

ns max

Pulse width of spike suppressed

1

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the falling

edge of SCL.

2

Cb is the total capacitance of one bus line in pF. tR and tF measured between 0.3 × VDD and 0.7 × VDD.

3

Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.

Timing Diagrams

SCLK

SYNC

DIN

DOUT

t1

t2

t4

t6

t5

t9

t8

t3

t7

t11

DB0

DB7

DB7*

DB6*

DB2*

DB1*

DB0*

t10

*DATA FROM PREVIOUS WRITE CYCLE

Figure 3. 3-Wire Serial Interface Timing Diagram

SDA

SCL

START

CONDITION

REPEATED

START

CONDITION

STOP

CONDITION

t8

t1

t7

t4

t5

t11

t2

t6

t10

t3

t4

t9

Figure 4. 2-Wire Serial Interface Timing Diagram