ADG714 datasheet(18/21 Pages) AD

18 / 21 page

ADG714/ADG715

Data Sheet

Rev. E | Page 18 of 21

Input Shift Register

The input shift register is eight bits wide. Figure 24 illustrates

the contents of the input shift register. Data is loaded into the

device as an 8-bit word under the control of a serial clock input,

SCL. The timing diagram for this operation is shown in Figure 4.

The 8-bit word consists of eight data bits, each controlling one

switch. MSB (Bit 7) is loaded ﬁrst.

Write Operation

When writing to the ADG715, the user begins with an address

byte and an R/W bit, after which the switch acknowledges that

it is prepared to receive data by pulling SDA low. This address

byte is followed by the 8-bit word. The write operation for the

switch is shown in Figure 25.

Read Operation

When reading data back from the ADG715, the user begins

with an address byte and an R/W bit, after which the switch

acknowledges that it is prepared to transmit data by pulling

SDA low. The readback operation is a single byte that consists of

the eight data bits in the input register. The read operation for

the switch is shown in Figure 26.

SCL

SDA

R/W

ACK

ADG715

ACK

ADG715

START

COND

MASTER

STOP

COND

MASTER

ADDRESS BYTE

DATA BYTE

Figure 25. ADG715 Write Sequence

SCL

SDA

R/W

ACK

ADG715

NO ACK

MASTER

START

COND

MASTER

STOP

COND

MASTER

ADDRESS BYTE

DATA BYTE

Figure 26. ADG715 Readback Sequence

ADG714 Datasheet(PDF) 18 Page - Analog Devices

ADG714 Datasheet(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

Datasheet Download

Link URL