HD404324FS datasheet(39/103 Pages) RENESAS

39 / 103 page

HD404054 Series/HD404094 Series

The on/off statuses of the output buffers are controlled by D-port data control registers (DCD0–DCD2:

$02C–$02E) that are mapped to memory addresses (figure 20).

Pins D

12 and D 13 are multiplexed with peripheral function pins STOPC and INT0, respectively.

The

peripheral function modes of these pins are selected by bits 2 and 3 (PMRC2, PMRC3) of port mode

R Ports (R0

0–RE0):

17 input/output pins and 6 input pins addressed in 4-bit units. Data is input to these

ports by the LAR and LBR instructions, and output from them by the LRA and LRB instructions. *Output

data is stored in the port data register (PDR) for each pin. The on/off statuses of the output buffers of the R

ports are controlled by R-port data control registers (DCR0–DCR4: $030–$034) that are mapped to

memory addresses (figure 20).

Pin R0

0 is are multiplexed with peripheral pin INT1 respectively.

The peripheral function modes of these

pins are selected by bit 0 (PMRB0) of port mode register B (PMRB: $024) (figure 21).

Pins R3

1–R32 are multiplexed with peripheral pins TOC and TOD respectively.

The peripheral function

modes of these pins are selected by bits 0–2 (TMC20–TMC22) of timer mode register C2 (TMC2: $014),

and bits 0–3 (TMD20–TMD23) of timer mode register D2 (TMD2: $015) (figures 23, and 24).

Pin R4

0 is multiplexed with peripheral pin EVND respectively.

The peripheral function modes of these

pins are selected by bit 1 (PMRC1) of port mode register C (PMRC: $025) (figure 22).

Pins R4

1–R43 are multiplexed with peripheral pins SCK1, SI1, and SO1, respectively.

The peripheral

function modes of these pins are selected by bit 3 (SM1A3) of serial mode register 1A (SM1A: $005), and

bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004), as shown in figures 25 and 26.

Ports RD

0 and RD1 are multiplexed with peripheral function pins COMP0 and COMP1, respectively.

The

function modes of these pins are selected by bit 3 (CER3) of the compare enable register (CER: $018)

(figure 27).

Port RE

0 is multiplexed with peripheral function pin VCref.

While functioning as VC

ref, do not use this pin

as an R port at the same time, otherwise, the MCU may malfunction.

Pull-Up or Pull-Down MOS Transistor Control: A program-controlled pull-up or pull-down MOS

transistor is provided for each input/output pin other than input-only pins D

12 and D 13. The on/off status of

all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off

status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding

pin—enabling on/off control of that pin alone (table 20 and figure 28).

The on/off status of each transistor and the peripheral function mode of each pin can be set independently.

How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be

connected to V

CC to prevent LSI malfunctions due to noise.

These pins must either be pulled up to V

CC by

their pull-up MOS transistors or by resistors of about 100 k

Ω or pulled down to GND by their pull-down

MOS transistors.

Note:

*If nonexisted bits of R ports is read, undifined data will be latched to accumulator (A) or the B

HD404324FS Datasheet(PDF) 39 Page - Renesas Technology Corp

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