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HD404324FS Datasheet(PDF) 59 Page - Renesas Technology Corp |
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HD404324FS Datasheet(HTML) 59 Page - Renesas Technology Corp |
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59 / 103 page  HD404054 Series/HD404094 Series 57 Selector 3 2 PER ø Input capture status flag (ICSF) Input capture error flag (ICEF) Timer D interrupt request flag (IFTD) Error control logic Edge detection logic Timer read register DU (TRDU) Timer read register DL (TRDL) Read signal Clock Timer counter D (TCD) Overflow System clock Edge detection control Prescaler S (PSS) Input capture timer control Timer mode register D1 (TMD1) Timer mode register D2 (TMD2) Edge detection selection register 2 (ESR2) EVND Figure 40-2 Block Diagram of Timer D (in Input Capture Timer Mode) |
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