HD404324FS datasheet(18/103 Pages) RENESAS

18 / 103 page

HD404054 Series/HD404094 Series

A block diagram of the interrupt control circuit is shown in figure 8, interrupt priorities and vector

addresses are listed in table 2, and interrupt processing conditions for the 6 interrupt sources are listed in

table 3.

An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the

interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to

that interrupt source.

The interrupt processing sequence is shown in figure 9 and an interrupt processing flowchart is shown in

figure 10. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The

IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack

during the second and third cycles, and the program jumps to the vector address to execute the instruction

in the third cycle.

Program the JMPL instruction at each vector address, to branch the program to the start address of the

interrupt program, and reset the IF by a software instruction within the interrupt program.

Table 2

Vector Addresses and Interrupt Priorities

Reset/Interrupt

Priority

Vector Address

RESET, STOPC*

—

$0000

INT

$0002

INT

$0004

Timer A

$0006

Not used

$0008

Timer C

$000A

Timer D

$000C

Serial 1

$000E

Note:

* The

STOPC interrupt request is valid only in stop mode.

HD404324FS Datasheet(PDF) 18 Page - Renesas Technology Corp