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HD404324FS Datasheet(PDF) 22 Page - Renesas Technology Corp |
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HD404324FS Datasheet(HTML) 22 Page - Renesas Technology Corp |
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22 / 103 page ![]() HD404054 Series/HD404094 Series 20 Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt processing and set by the RTNI instruction, as listed in table 4. Table 4 Interrupt Enable Flag (IE: $000, Bit 0) IE Interrupt Enabled/Disabled 0 Disabled 1 Enabled External Interrupts ( INT 0, INT1): Two external interrupt signals. External Interrupt Request Flags (IF0, IF1: $000, $001): IF0 and IF1 are set the falling of signals input to INT 0 and INT1 as listed in table 5. Table 5 External Interrupt Request Flags (IF0, IF1: $000, $001) IF0, IF1 Interrupt Request 0No 1 Yes External Interrupt Masks (IM0, IM1: $000, $001): Prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as listed in table 6. Table 6 ExternalInterrupt Masks (IM0, 1M1: $000, $001) IM0, IM1 Interrupt Request 0 Enabled 1 Disabled (masked) Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in table 7. Table 7 Timer A Interrupt Request Flag (IFTA: $001, Bit 2) IFTA Interrupt Request 0No 1 Yes |
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