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HD404324FS Datasheet(PDF) 72 Page - Renesas Technology Corp |
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HD404324FS Datasheet(HTML) 72 Page - Renesas Technology Corp |
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72 / 103 page  HD404054 Series/HD404094 Series 70 Transfer completion (IFS1 1) Interrupts inhibited IFS1 0 SM1A write IFS1 = 1 Transmit clock error processing Normal termination ← ← Yes No Transmit clock error detection flowchart Transmit clock error detection procedures State Transmit clock wait state Transfer state Transfer state Transmit clock wait state Noise Transfer state has been entered by the transmit clock error. When SM1A is written, IFS1 is set. Flag set because octal counter reaches 000. Flag reset at transfer completion. SM1A write 12 3 4 56 78 SCK pin (input) IFS1 1 Figure 52 Transmit Clock Error Detection |
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