HD404324FS datasheet(11/103 Pages) RENESAS

11 / 103 page

HD404054 Series/HD404094 Series

Bit 3

Bit 2

Bit 1

Bit 0

IMTA

(IM of timer A)

IFTA

(IF of timer A)

IM1

(IM of

INT1)

IF1

(IF of

INT1)

IMTC

(IM of timer C)

IFTC

(IF of timer C)

IMS1

(IM of serial

interface 1)

IFS1

(IF of serial

interface 1)

IMTD

(IM of timer D)

IFTD

(IF of timer D)

$000

$001

$002

$003

Interrupt control bits area

IM0

(IM of

INT0)

IF0

(IF of

INT0)

RSP

(Reset SP bit)

(Interrupt

enable flag)

ICSF

(Input capture

status flag)

$020

$021

WDON

(Watchdog

on flag)

ICEF

(Input capture

error flag)

RAME

(RAM enable

flag)

Not used

IF:

IM:

IE:

SP:

Interrupt request flag

Interrupt mask

Interrupt enable flag

Stack pointer

Bit 3

Bit 2

Bit 1

Bit 0

Not used

Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas

ICSF

ICEF

RAME

RSP

WDON

Not used

SEM/SEMD

REM/REMD

TM/TMD

Allowed

Not executed

Allowed

Not executed

Allowed

Inhibited

Allowed

Not executed

Inhibited

Not executed

Inhibited

Note: WDON is reset by MCU reset or by

STOPC enable for stop mode cancellation.

If the TM or TDM instruction is executed for the inhibited bits or non-existing bits,

the value in ST becomes invalid.

Figure 4 Usage Limitations of RAM Bit Manipulation Instructions

HD404324FS Datasheet(PDF) 11 Page - Renesas Technology Corp

HD404324FS Datasheet(HTML) 11 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL