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HD404374FT Datasheet(PDF) 127 Page - Renesas Technology Corp |
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HD404374FT Datasheet(HTML) 127 Page - Renesas Technology Corp |
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127 / 161 page ![]() HD404374/HD404384/HD404389/HD404082/HD404084 Series Rev.5.00, Sep.11.2003, page 127 of 161 Instruction Set The MCU Series has 101 instructions, classified into the following 10 groups: • Immediate instructions • Register-to-register instructions • RAM addressing instructions • RAM register instructions • Arithmetic instructions • Compare instructions • RAM bit manipulation instructions • ROM addressing instructions • Input/output instructions • Control instructions The functions of these instructions are listed in tables 30 to 39, and an opcode map is shown in table 40. Table 30 Immediate Instructions Operation Mnemonic Operation Code Function Status Words/ Cycles Load A from immediate LAI i 1 0 0 0 1 1 i 3 i 2 i 1 i 0 i → A 1/1 Load B from immediate LBI i 1 0 0 0 0 0 i 3 i 2 i 1 i 0 i → B 1/1 Load memory from immediate LMID i,d 0 1 1 0 1 0 i 3 i 2 i 1 i 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 i → M 2/2 Load memory from immediate, increment Y LMIIY i 1 0 1 0 0 1 i 3 i 2 i 1 i 0 i → M, Y + 1 → Y NZ 1/1 Table 31 Register-Register Instructions Operation Mnemonic Operation Code Function Status Words/ Cycles Load A from B LAB 0 0 0 1 0 0 1 0 0 0 B → A 1/1 Load B from A LBA 0 0 1 1 0 0 1 0 0 0 A → B 1/1 Load A from W LAW 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W → A 2/2* Load A from Y LAY 0 0 1 0 1 0 1 1 1 1 Y → A 1/1 Load A from SPX LASPX 0 0 0 1 1 0 1 0 0 0 SPX → A 1/1 Load A from SPY LASPY 0 0 0 1 0 1 1 0 0 0 SPY → A 1/1 Load A from MR LAMR m 1 0 0 1 1 1 m 3 m2 m1 m0 MR (m) → A 1/1 Exchange MR and A XMRA m 1 0 1 1 1 1 m 3 m2 m1 m0 MR (m) ↔ A 1/1 Note: * The assembler automatically provides an operand for the second word of the LAW instruction. |
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