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SH7136 Datasheet(PDF) 167 Page - Renesas Technology Corp |
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SH7136 Datasheet(HTML) 167 Page - Renesas Technology Corp |
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167 / 1160 page  Section 7 User Break Controller (UBC) Rev. 2.00 Sep. 10, 2008 Page 141 of 1130 REJ09B0402-0200 7.3.12 Execution Times Break Register (BETR) BETR is a 16-bit readable/writable register. When the execution-times break condition of channel B is enabled, this register specifies the number of execution times to make the break. The maximum number is 2 12 – 1 times. When a break condition is satisfied, it decreases BETR. A user break interrupt is requested when the break condition is satisfied after BETR becomes H'0001. Bit: Initial value: R/W: 15 14 13 12 11 10 987654321 0 0000000000000000 RRRR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - - - - BET[11:0] Bit Bit Name Initial Value R/W Description 15 to 12 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 BET[11:0] All 0 R/W Number of Execution Times |
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