SH7136 datasheet(164/1160 Pages) RENESAS

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Section 7 User Break Controller (UBC)

Rev. 2.00 Sep. 10, 2008 Page 138 of 1130

REJ09B0402-0200

Bit

Bit Name

Initial

Value

R/W

Description

SCMFCA

R/W

L Bus Cycle Condition Match Flag A

When the L bus cycle condition in the break conditions

set for channel A is satisfied, this flag is set to 1. In

order to clear this flag, write 0 into this bit.

0: The L bus cycle condition for channel A does not

match

1: The L bus cycle condition for channel A matches

SCMFCB

R/W

L Bus Cycle Condition Match Flag B

When the L bus cycle condition in the break conditions

set for channel B is satisfied, this flag is set to 1. In

order to clear this flag, write 0 into this bit.

0: The L bus cycle condition for channel B does not

match

1: The L bus cycle condition for channel B matches

SCMFDA

R/W

I Bus Cycle Condition Match Flag A

When the I bus cycle condition in the break conditions

set for channel A is satisfied, this flag is set to 1. In

order to clear this flag, write 0 into this bit.

0: The I bus cycle condition for channel A does not

match

1: The I bus cycle condition for channel A matches

SCMFDB

R/W

I Bus Cycle Condition Match Flag B

When the I bus cycle condition in the break conditions

set for channel B is satisfied, this flag is set to 1. In

order to clear this flag, write 0 into this bit.

0: The I bus cycle condition for channel B does not

match

1: The I bus cycle condition for channel B matches

PCTE

R/W

PC Trace Enable

0: Disables PC trace

1: Enables PC trace

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