SH7136 datasheet(162/1160 Pages) RENESAS

162 / 1160 page

Section 7 User Break Controller (UBC)

Rev. 2.00 Sep. 10, 2008 Page 136 of 1130

REJ09B0402-0200

7.3.11

Break Control Register (BRCR)

BRCR sets the following conditions:

1. Specifies whether channels A and B conditions are used as two independent conditions or as

the sequential condition.

2. Specifies whether a user break is set before or after instruction execution.

3. Specifies whether to include the number of execution times in channel B comparison

conditions.

4. Specifies whether to include data bus in channels A and B comparison conditions.

5. Enables PC trace.

6. Selects the pulse width of the

UBCTRG output.

7. Specifies whether to request a user break interrupt on a match of channels A and B comparison

conditions.

BRCR is a 32-bit readable/writable register that has break conditions match flags and bits for

setting a variety of break conditions.

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

987654321

0000000000000000

RRRRRRRRRR

R/W

0000000000000000

R/W

----------

UTRGW[1:0]

UBIDB

UBIDA

SCM

FCA

SCM

FCB

SCM

FDA

SCM

FDB

PCTE

PCBA

DBEA

PCBB

DBEB

SEQ

ETBE

SH7136 Datasheet(PDF) 162 Page - Renesas Technology Corp

SH7136 Datasheet(HTML) 162 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL