SH7136 datasheet(160/1160 Pages) RENESAS

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Section 7 User Break Controller (UBC)

Rev. 2.00 Sep. 10, 2008 Page 134 of 1130

REJ09B0402-0200

7.3.10

Break Bus Cycle Register B (BBRB)

BBRB is a 16-bit readable/writable register, which specifies (1) bus master for I bus cycle, (2) L

bus cycle or I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size

in the break conditions of channel B.

Bit:

Initial value:

R/W:

987654321

0000000000000000

RRRRR

R/W

CPB[2:0]

IDB[1:0]

CDB[1:0]

RWB[1:0]

SZB[1:0]

Bit

Bit Name

Initial

Value

R/W

Description

15 to 11



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

10 to 8

CPB[2:0]

000

R/W

Bus Master Select B for I Bus

Select the bus master when the I bus is selected as

the bus cycle of the channel B break condition.

However, when the L bus is selected as the bus cycle,

the setting of the CPB2 to CPB0 bits is disabled.

000: Condition comparison is not performed

xx1: The CPU cycle is included in the break condition

x1x: Setting prohibited

1xx: The DTC cycle is included in the break condition

7, 6

CDB[1:0]

R/W

L Bus Cycle/I Bus Cycle Select B

Select the L bus cycle or I bus cycle as the bus cycle

of the channel B break condition.

00: Condition comparison is not performed

01: The break condition is the L bus cycle

10: The break condition is the I bus cycle

11: The break condition is the L bus cycle

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