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HD64F36034 Datasheet(PDF) 81 Page - Renesas Technology Corp |
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HD64F36034 Datasheet(HTML) 81 Page - Renesas Technology Corp |
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81 / 592 page  Section 3 Exception Handling Rev. 4.00 Mar. 15, 2006 Page 49 of 556 REJ09B0026-0400 Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. • Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling starts. Exception handling is the same as exception handling by the RES pin. • Trap Instruction Exception handling starts when a trap instruction (TRAPA) is executed. The TRAPA instruction generates a vector address corresponding to a vector number from 0 to 3, as specified in the instruction code. Exception handling can be executed at all times in the program execution state, regardless of the setting of the I bit in CCR. • Interrupts External interrupts other than NMI and internal interrupts other than address break are masked by the I bit in CCR, and kept masked while the I bit is set to 1. Exception handling starts when the current instruction or exception handling ends, if an interrupt request has been issued. |
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