HD64F36034 datasheet(84/592 Pages) RENESAS

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Section 3 Exception Handling

Rev. 4.00 Mar. 15, 2006 Page 52 of 556

REJ09B0026-0400

3.2

Interrupts are controlled by the following registers.

• Interrupt edge select register 1 (IEGR1)

• Interrupt edge select register 2 (IEGR2)

• Interrupt enable register 1 (IENR1)

• Interrupt enable register 2 (IENR2)

• Interrupt flag register 1 (IRR1)

• Interrupt flag register 2 (IRR2)

• Wakeup interrupt flag register (IWPR)

3.2.1

Interrupt Edge Select Register 1 (IEGR1)

IEGR1 selects the direction of an edge that generates interrupt requests of pins

NMI and IRQ3 to

IRQ0.

Bit

Bit Name

Initial

Value

R/W

Description

NMIEG

R/W

NMI Edge Select

0: Falling edge of

NMI pin input is detected

1: Rising edge of

NMI pin input is detected

6 to 4



All 1



Reserved

These bits are always read as 1.

IEG3

R/W

IRQ3 Edge Select

0: Falling edge of

IRQ3 pin input is detected

1: Rising edge of

IRQ3 pin input is detected

IEG2

R/W

IRQ2 Edge Select

0: Falling edge of

IRQ2 pin input is detected

1: Rising edge of

IRQ2 pin input is detected

IEG1

R/W

IRQ1 Edge Select

0: Falling edge of

IRQ1 pin input is detected

1: Rising edge of

IRQ1 pin input is detected

IEG0

R/W

IRQ0 Edge Select

0: Falling edge of

IRQ0 pin input is detected

1: Rising edge of

IRQ0 pin input is detected

HD64F36034 Datasheet(PDF) 84 Page - Renesas Technology Corp

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