HD64F36034 datasheet(30/592 Pages) RENESAS

30 / 592 page

Rev. 4.00 Mar. 15, 2006 Page xxx of xxxii

Table 7.3

System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is

Possible................................................................................................................... 98

Table 7.4

Reprogram Data Computation Table .................................................................... 102

Table 7.5

Additional-Program Data Computation Table...................................................... 102

Table 7.6

Programming Time............................................................................................... 102

Table 7.7

Flash Memory Operating States............................................................................ 107

Section 10 Timer B1

Table 10.1

Pin Configuration.................................................................................................. 144

Table 10.2

Timer B1 Operating Modes .................................................................................. 148

Section 11 Timer V

Table 11.1

Pin Configuration.................................................................................................. 151

Table 11.2

Clock Signals to Input to TCNTV and Counting Conditions ............................... 153

Section 12 Timer Z

Table 12.1

Timer Z Functions ................................................................................................ 164

Table 12.2

Pin Configuration.................................................................................................. 168

Table 12.3

Initial Output Level of FTIOB0 Pin...................................................................... 200

Table 12.4

Output Pins in Reset Synchronous PWM Mode................................................... 206

Table 12.5

Table 12.6

Output Pins in Complementary PWM Mode........................................................ 210

Table 12.7

Table 12.8

Section 14 Serial Communication Interface 3 (SCI3)

Table 14.1

Channel Configuration.......................................................................................... 252

Table 14.2

Pin Configuration.................................................................................................. 254

Table 14.3

Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 262

Table 14.3

Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 264

Table 14.3

Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ...... 266

Table 14.4

Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 267

Table 14.5

Examples of BRR Settings for Various Bit Rates

(Clocked Synchronous Mode) (1)......................................................................... 268

Table 14.5

Examples of BRR Settings for Various Bit Rates

(Clocked Synchronous Mode) (2)......................................................................... 269

Table 14.6

SSR Status Flags and Receive Data Handling ...................................................... 275

Table 14.7

SCI3 Interrupt Requests........................................................................................ 291

Section 15 Controller Area Network for Tiny (TinyCAN)

Table 15.1

Pin Configuration.................................................................................................. 297

Table 15.2

Settable Values in BCR ........................................................................................ 325

Table 15.3

Settable Values for TSG1 and TSG2 in BCR1 ..................................................... 326

HD64F36034 Datasheet(PDF) 30 Page - Renesas Technology Corp

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