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HD64F36034 Datasheet(PDF) 22 Page - Renesas Technology Corp |
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HD64F36034 Datasheet(HTML) 22 Page - Renesas Technology Corp |
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22 / 592 page  Rev. 4.00 Mar. 15, 2006 Page xxii of xxxii Figure 5.5 Typical Connection to Ceramic Resonator.................................................................. 75 Figure 5.6 Example of External Clock Input ................................................................................ 75 Figure 5.7 Example of Incorrect Board Design ............................................................................ 76 Section 6 Power-Down Modes Figure 6.1 Mode Transition Diagram ........................................................................................... 82 Section 7 ROM Figure 7.1 Flash Memory Block Configuration............................................................................ 90 Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode............................ 99 Figure 7.3 Program/Program-Verify Flowchart ......................................................................... 101 Figure 7.4 Erase/Erase-Verify Flowchart ................................................................................... 104 Section 9 I/O Ports Figure 9.1 Port 1 Pin Configuration............................................................................................ 111 Figure 9.2 Port 2 Pin Configuration............................................................................................ 116 Figure 9.3 Port 5 Pin Configuration............................................................................................ 120 Figure 9.4 Port 6 Pin Configuration............................................................................................ 126 Figure 9.5 Port 7 Pin Configuration............................................................................................ 131 Figure 9.6 Port 8 Pin Configuration............................................................................................ 135 Figure 9.7 Port 9 Pin Configuration............................................................................................ 137 Figure 9.8 Port B Pin Configuration...........................................................................................141 Section 10 Timer B1 Figure 10.1 Block Diagram of Timer B1.................................................................................... 143 Section 11 Timer V Figure 11.1 Block Diagram of Timer V ..................................................................................... 150 Figure 11.2 Increment Timing with Internal Clock .................................................................... 157 Figure 11.3 Increment Timing with External Clock................................................................... 157 Figure 11.4 OVF Set Timing ...................................................................................................... 157 Figure 11.5 CMFA and CMFB Set Timing................................................................................ 158 Figure 11.6 TMOV Output Timing ............................................................................................ 158 Figure 11.7 Clear Timing by Compare Match............................................................................ 158 Figure 11.8 Clear Timing by TMRIV Input ............................................................................... 159 Figure 11.9 Pulse Output Example............................................................................................. 159 Figure 11.10 Example of Pulse Output Synchronized to TRGV Input....................................... 160 Figure 11.11 Contention between TCNTV Write and Clear ...................................................... 161 Figure 11.12 Contention between TCORA Write and Compare Match ..................................... 162 Figure 11.13 Internal Clock Switching and TCNTV Operation ................................................. 162 |
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