HD64F36034 datasheet(103/592 Pages) RENESAS

103 / 592 page

Section 4 Address Break

Rev. 4.00 Mar. 15, 2006 Page 71 of 556

REJ09B0026-0400

4.2

Operation

When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an

interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the

address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt

request is accepted, interrupt exception handling starts after the instruction being executed ends.

The address break interrupt is not masked by the I bit in CCR of the CPU.

Figures 4.2 show the operation examples of the address break interrupt setting.

NOP

instruc-

tion

prefetch

• ABRKCR = H'80

• BAR = H'025A

Program

0258

025A

025C

0260

0262

NOP

MOV.W @H'025A,R0

NOP

0258

Address

bus

Interrupt

request

025A

025C

025E

SP-2

SP-4

NOP

instruc-

tion

prefetch

MOV

instruc-

tion 1

prefetch

MOV

instruc-

tion 2

prefetch

Internal

processing

Stack save

Interrupt acceptance

Underline indicates the address

to be stacked.

When the address break is specified in instruction execution cycle

Figure 4.2 Address Break Interrupt Operation Example (1)

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